1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to a semiconductor device including a semiconductor memory, in which a PN junction is formed at a charge-storage boundary, the semiconductor memory having a lower wiring resistance while preventing a junction leakage current.
2. Background Art
Recently, semiconductor memories having a charge-storage region in a cell have been studied in order to achieve high-integration.
An FBC (Floating-Body Cell) memory is known as such a semiconductor device, which was introduced during a lecture given in the ISSCC 2002 (International Solid-State Circuit Conference 2002, held in San Francisco, Mar. 3–7, 2002). The details of this memory were clarified in “ISSCC 2002/SESSION 9/DRAM AND FERROELCTRIC MEMORIES/9.1/Memory Design Using One-Transistor Gain Cell SOI/Takashi Ohasawa et al.”.
The FBC memory has a cell structure including an MOS transistor formed on an SOI (Silicon On Insulator), a charge-storage region for storing charge being formed under the transistor.
In such an FBC memory, especially one having a PN junction at the boundary of a charge-storage region, there is a case where a polycrystalline silicon plug is used as a plug or wiring on the PN junction in order to decrease a junction leakage current. However, with a polycrystalline silicon plug, it is difficult to achieve a lower wiring resistance.
FIG. 11 is a plan view of an FBC memory, which is an example of a semiconductor device known to the present inventor, and FIG. 12 is a sectional view taken along line A—A of FIG. 11.
In these drawings, “UC” denotes a unit cell constituting a MOS transistor. As shown in FIG. 12, the SOI structure of the FBC memory includes a support substrate 1 formed of p-type silicon, an embedded oxide layer (insulating layer) 2 formed on the support substrate 1 with an n-type well 1a provided therebetween, and a silicon layer 3 formed on the embedded oxide layer 2. The silicon layer 3 includes source and drain regions (diffusion layer regions) 4, 4, and a channel region 5 sandwiched by the source and drain regions 4, 4. A source line SL or a bit line BL is formed above the diffusion layer regions 4, 4, and a word line (gate) WL is formed above the channel region 5 with a gate insulating layer 7 located therebetween. The diffusion layer 4 (D=drain) and the bit line BL are connected by a contact plug CP. The contact plug CP and the source line SL are formed of polycrystalline silicon. The source line SL is grounded. In these drawings, “8” denotes an interlayer dielectric film (BPSG).
In the FBC memory having the aforementioned structure, when a current flows from the diffusion layer region 4 (D) to the diffusion layer region 4 (S=source) via the channel region 5, hot holes are generated within the channel region 5. The hot holes are stored in the channel region 5. That is to say, the channel region 5 serves as a data (hole) storage capacitor, i.e., charge-storage region, to perform a memory operation. Thus, the charge-storage region is located under the gate (word line WL) of the unit cell UC, i.e., a MOS transistor. The FBC memory has an advantageous effect that the circuit area can be considerably decreased, thereby achieving high-integration.
However, the data storage time of an FBC memory is shorter than that of a conventional DRAM. One way of extending the data storage time may be to decrease a junction leakage current flowing through the diffusion layer regions 4. At the same time, since it is necessary to generate hot holes in the charge-storage region, it would be better if the resistance of the bit line BL and the source line SL connected to the ground were lower. FIGS. 13 and 14 show an example of an FBC memory in which a source line SL and a contact plug CP connecting to a bit line BL, which are formed of polycrystalline silicon, are connected via a self-aligned silicide, thereby achieving a lower wiring resistance. FIGS. 13 and 14 are sectional views showing different portions of a single semiconductor device. In particular, FIG. 13 shows an FBC cell portion of, and FIG. 14 shows an FBC periphery circuit portion. As shown in these drawings, a lower wiring resistance is achieved by applying a self-aligned silicide process to an electrode formed of polycrystalline silicon so as to form self-aligned silicide portions 11 at the contact portions and the electrical connection portions of a bit line BL, a word line WL, and a source line SL. In these drawings, “12”, “13”, and “14” denote gate sidewalls.
As is apparent from FIG. 13, however, with the aforementioned structure, the surface of a (monocrystal) silicon layer 3 is directly subjected to the self-aligned silicide process. Accordingly, an interface reaction occurs or a crystal defect is generated at the junction portion, resulting in a high junction leakage current. As a result, a problem arises in the charge storage capacity, which is important to the memory operation.
Since the conventional semiconductor device known to the present inventor has the aforementioned structure, an attempt to decrease the wiring resistance in order to increase the hot hole storage capacity in the chare-storage region results in the increase in junction leakage current, thereby degrading the charge storage capacity.